Scalable subsystem architecture having integrated cooling channels

ABSTRACT

A method for building scalable electronic subsystems is described. Stackable modules employ copper substrates with solder connections between modules, and a ball grid array interface is provided at the bottom of the stack. A cooling channel is optionally provided between each pair of modules. Each module is re-workable because all integrated circuit attachments within the module employ re-workable flip chip connectors. Also, defective modules can be removed from the stack by directing hot inert gas at externally accessible solder connections.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of pending U.S. patent application Ser.No. 11/495,954 filed Jul. 27, 2006, which claims priority to U.S.Provisional Patent Application No. 60/704,774 filed Aug. 1, 2005. Theseapplications are each incorporated by reference herein.

FIELD OF THE INVENTION

This invention relates to integration of semiconductor chips intoelectronic systems, and more particularly to a scalable subsystem havingintegrated cooling channels.

DESCRIPTION OF THE RELATED ART

Over the last 40 years transistor density in silicon integrated circuit(IC) chips has increased by a factor greater than 100,000; thisphenomenon is known as Moore's Law. Meanwhile, the ability to integratesilicon chips into systems has progressed relatively slowly. Packagedevelopment can be traced from printed circuit boards (PCBs) havingplated through holes (PTHs) around 1970. Surface mount technology (SMT)has followed, also multi-chip modules (MCMs), and systems in package(SIPs). The slow rate of development of integration methods comparedwith silicon fabrication has resulted in an integration gap; this gaphas dimensions of cost, performance, cooling, and scalability.

The 2003 International Technology Roadmap for Semiconductors (ITRS)shows packaging costs for microprocessor circuits exceeding chip costsin 2010. Digital IC chips can now operate at signaling rates of 10 Gbpswhile many packages do not support speeds greater than around 200 Mpbs.Cooling has become critical. Modem servers typically have bulky finnedaluminum heat sinks surrounding each of the processors. This increasesthe volume of the server units with attendant cost increases andperformance decreases. Recent microprocessor chips dissipate as much as150 W each. Cooling costs for a 30,000 square foot data center arereported at $8 million per year. Scalability has not been much discussedat the system level, apart from providing servers in a blade form factorfor higher packaging density and user convenience. Generally, system orsubsystem scalability is difficult if multiple component types andpackages are employed.

Electrical connections to an IC chip have typically occurred on thefront side of the chip where the active circuits and bonding pads arelocated, while cooling has been provided at the back side. Thermalinterface materials (TIMs) such as thermal grease have been used betweenthe back side of the die and its heat sink. When thermal grease is used,it is typically the highest impedance element in the thermal path.

SUMMARY OF THE INVENTION

IC modules are described wherein IC chips are attached tointerconnection substrates using flexible and re-workable pillar in well(PIW) attachments. Each interconnection substrate includes high densityinterconnect (HDI) circuits fabricated on a sheet of copper. A test chipis provided in each module so it can be tested and reworked as required.Modules are stacked to form scalable subsystems using ball grid array(BGA) connectors, with cooling channels provided optionally between eachpair of modules. A gas or liquid coolant is circulated in the coolingchannels.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects of the invention will be more clearlyunderstood from the accompanying drawings and description of theinvention:

FIG. 1 is a cross-sectional view of a stacked subsystem of the currentinvention, including embedded cooling channels.

FIG. 2A is an enlarged cross-sectional view of region A of FIG. 1.

FIG. 3 is a cross-sectional view corresponding to section AA of FIG. 2.

FIG. 4 is similar to FIG. 3, except some solder balls have been replacedwith fiber optic connections.

FIG. 5 shows an expanded cross-sectional view of a fiber optic connectorof FIG. 4.

FIG. 6 shows in cross-section a further expanded view of a fiber opticconnector that employs both heat bumps and I/O bumps.

FIG. 7 depicts in cross-section a fiber optic connection that does notrequire a glass window.

FIG. 8 shows in cross-section a stack of subsystems, with a fiber opticconnection to each subsystem.

FIG. 9 illustrates in cross-section the use of a semiconductor plugdevice in a module.

FIG. 10 shows an expanded schematic cross-sectional view of the plugdevice of FIG. 9.

FIG. 11 is a schematic view of section BB of FIG. 2, showing aninterface between a chip and a substrate that includes a mixed array ofI/O bumps and heat bumps.

FIG. 12 is an expanded cross-sectional view of section CC of FIG. 11.

FIG. 13 is a further expanded cross-sectional view of Detail D of FIG.12.

FIG. 14 is an expanded cross-sectional view showing the use of a dampinglayer.

FIG. 15 is a top view of a square copper panel showing a layout ofmultiple copper substrates on a circular copper wafer to be separatedfrom the square panel.

FIG. 16A-16F depicts in cross-section a series of process steps forfabricating a hermetic copper substrate of the current invention havingglass-isolated copper feedthroughs.

FIG. 17A-17P depicts in cross-section a series of process steps forfabricating a 5-layer interconnection circuit plus and a well layer onthe copper substrate of FIG. 15D, and also forming a solder ball at eachfeed through, and assembling a chip on the interconnection circuit.

FIG. 18 shows a subsystem stack in cross-section, including a directedsource of hot inert gas for removing a defective module.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments of the present invention are described hereinafterwith reference to the figures. It should be noted that the figures areonly intended to facilitate the description of specific embodiments ofthe invention. They are not intended as an exhaustive description of theinvention or as a limitation on the scope of the invention. In addition,an aspect described in conjunction with a particular embodiment of thepresent invention is not necessarily limited to that embodiment and canbe practiced in any other embodiments. For instance, the preferredembodiment describes cooling of the high power laser diodes in theelectro-optic chip using heat bumps at the front face of the chip.However, additional cooling may be applied through the back face of thechip, using a thicker chip or a copper slug, as described relative toother circuit elements of the current invention.

A preferred embodiment of the current invention is a stacked system orsubsystem employing modules comprising copper substrates and arrays offlipped chips, with inter-stack cooling channels provided between eachpair of modules in the stack. Conventional system components such asPCBs and discrete packages are eliminated. The system is assembled fromsemiconductor chips and copper substrates having interconnectioncircuits fabricated thereon. Preferably all of the integrated circuittypes including digital, analog, RF, integrated passives, optical, andelectro-optical are provided on IC chips that attach using the same typeof PIW connector.

The PIW connector employs a pillar or a bump inserted into a well filledwith conductive material. It is described in U.S. Pat. No. 6,881,609 forthe case of gold stud bumps and solder as the conductive material in thewells. The bumps are usually provided on the IC chips and the wells areprovided on the substrate to which the chips are attached, although thereverse can also be employed. The current description of PIW employs aflexible copper pillar for the bump instead of a gold stud bump. Thepillar is formed by electro-deposition as a thin wire-like elementhaving flexibility for relieving stress at the interface between chipand substrate. By providing this stress relief using flexible pillars,columns, mesas, or bumps, the typical requirement for an epoxy underlayer is avoided; this makes easy rework possible. Testing of known gooddie (KGD) can be accomplished at full power and full speed by fillingthe wells with a conductive dry powder. Modules including multiple chipscan be assembled and tested in this temporary form of the finalassembly, with convenient replacement of any chips that prove defective.For production units, a semi-permanent connection is made by heating thedry powder to form solder; this can be accomplished in one step for anentire subsystem assembly. Even the melted solder connections can bereworked if necessary. This is done be selectively applying heat to meltthe solder attaching a defective component. The defective component iswithdrawn from the wells, the remaining solder is sucked out of thewells, the wells are refilled and a replacement chip is attached. Byusing these temporary and semi-permanent connections, complex assemblieswith 100 or more chips can be assembled with 100% assembly yield. Thisavoids rejection of modules or subsystems due to imperfect yield of thecomponent chips. Thus a cost benefit is achieved for modules having upto approximately 6 chips where the compound yield is satisfactory, andan enabling technology is achieved for extending module complexity tomodules having 100 chips or more, for example.

For complex flip chip assemblies it is difficult or impossible to testthem at full power and full speed through a cable to an external testbox. Use of a typical test connector and cable tends to negate theminiaturization advantages of flip chip. Also, it is difficult to driveand sense high speed signals through conventional cables and connectorsdue to their parasitic inductance and capacitance, particularly as chiptechnology progresses toward lower power supplies and reduced noisemargins. For the systems described herein it is preferable to providetest chips resident in the modules; they will include high speedsampling circuits and comparators and an interface to a test supportcomputer. This testing approach is described in co-pending U.S. patentapplication Ser. No. 10/448,611, and is incorporated herein in itsentirety by reference.

The current invention provides an option for providing a mixed array offlip chip connectors at the interface between each chip and itsunderlying substrate. The mixed array provides both input/output (I/O)capabilities and heat sinking capabilities on the active (front) side ofthe IC chip. A regular array of bumps (pillars) can be formed in rowsand columns to create a sea of bumps, of which selected ones are usedfor I/O, and the others are used for heat-sinking. Modern microprocessorchips may require 2,000 leads or more, combining both signal and powerpins. The PIW connectors can be configured in a small size that willsupport digital signaling rates of around 20 Gbps.

FIG. 1 shows a stacked electronic assembly (subsystem) 10 of the currentinvention. Subsystem 10 includes hermetic modules 11 containing IC chips12. Modules 11 at different levels in the stack may be similar toperform a similar function, or may be different to perform differentfunctions. Modules 11 are preferably built on copper substrates 14 andare preferably separated by inter-stack cooling channels 15 throughwhich a coolant may flow. Modules 11 and cooling channels 15 arepreferably hermetically sealed (hermetic), to prevent any moisturereaching IC chips 12 as well as to contain the coolant without leakage.As examples, the coolant fluid may be air or water or liquid metal.Cooling channels 15 may be provided between each pair of modules 11, ormay be selectively included between high power modules, and not includedbetween low power modules. Subsystem 10 may interface with a PCB orother electronic component using solder balls 16 arranged to form a ballgrid array (BGA). The BGA interface provides power and signal I/O tostacked assembly 10, and the stacked BGA connectors 17 providedistribution throughout subsystem 10. PIW connectors may be used inplace of the BGA connectors, although a sealing type of connection isrequired to contain the coolant in cooling channels 15, and this istypically achieved using solder. Thus, a hybrid of PIW electricalconnectors combined with solder-type sealing connections may beemployed. A typical height H 18 for subsystem 10 including sixteenmodules 11 is 60 mm with a typical width dimension W 19 of 50 mm. Anexample subsystem 10 may be a 64-way computer server wherein each module11 contains around 80° C. chips and implements a 4-way server. The suiteof IC chips within module 11 may include processors, I/O and legacycontrollers, memory chips of various types (flash and DDR RAM forexample), power distribution chips, one or more test chips, andintegrated passives. Compared with servers that are currently availablein a blade format (like the IBM HS40 which is a 4-way blade server),modules 11 are smaller and lighter by a factor of more than 100. As willbe further explained, modules 11 and subsystem 10 are also testable andrepairable, including repair of any chip in any module.

Subsystem 10 will be more reliable than conventional subsystems becauseof its electrical, mechanical, and thermal design. This is brieflydescribed here in the context of FIG. 1 and further elaborated in thefollowing paragraphs. A new type of flip chip connector (the PIWconnector) is used to attach each of the I/O chips such as 12. A similarPIW connector is used for both I/O and for heat extraction. The PIWconnector includes a slender copper column (bump) that is flexibleenough to relieve shear stresses at the chip/substrate interface. Theflexibility (compliance) of the copper column eliminates reliabilityissues such as cracking of the solder joints due to thermally inducedmechanical stress. Also, epoxy under fill is not required and this is animportant enabler of an effective rework strategy, for replacing acomponent that proves to be defective. The copper base plates provide arugged mechanical design, yet compliance in the flexible copper bumpsmakes the modules resistant to vibration and shock damage. The thermaldesign includes options for cooling high thermal fluxes, to be furtherdescribed. Tight control of junction temperatures leads to increasedcircuit reliability which is a strong function of peak operatingtemperature. Finally, by eliminating conventional cables and connectors,subsystem reliability is further improved.

The scalability of subsystem 10 is apparent from its modularconstruction; the stacking unit is a 4-way server in the preferredembodiment. It can be envisaged that a 256-way server would comprise astack having four times the height of subsystem 10, for example. It isanticipated that such a 256-way server would require more I/O than a64-way server; in this case the footprint may be increased,accommodating more I/O at the BGA interface. Since solder bumps andcopper feedthroughs have high current capacity, the number of BGAconnectors needed for distributing power may not need to increase,allowing the additional pins to be used for I/O. As an alternativesolution that will accommodate high bandwidth signals, fiber opticcommunication ports will be described in reference to FIG. 4 throughFIG. 8.

Compared with a typical electronic subsystem of today, the usual printedcircuit boards and discrete packages have been eliminated. Subsystem 10has been assembled from IC chips and copper substrates withinterconnection circuits that will be further described. This requiresthat all circuit components be provided in the form of IC chips,including integrated devices like computing cores, memory chips, powerdistribution chips, and integrated passives, as well as discrete devicessuch as resistors, capacitors, inductors, power diodes and powertransistors. It also requires innovations in test, assembly and rework,as will be further described. However, elimination of conventionalpackages and boards reduces cost. The board of the current invention canbe viewed as the combination of a high density interconnection (HDI)circuit and a heat dissipation device. Other manufacturing costadvantages are achievable using new testing and rework methods, to befurther described.

Because of their small size, the I/O connectors will have a lowinductance of approximately 0.1 nH, and this will enable digitalsignaling rates of around 20 Gbps as well as RF connections operating atfrequencies up to around 10 GHz.

FIG. 2 is an expanded cross-sectional view of region A of FIG. 1. Itdetails a portion of module 11, employing copper substrates 14. Coolingchannel 15 is shown, and solder ball 16 of a BGA interface. Copperfeedthrough 21 is isolated from copper substrate 14 by a glass seal 22,to be further described. IC chips such as 12 b are mounted using a flipchip attachment to interconnection circuit 23 a, to be furtherdescribed. If the backside of a chip requires a bias voltage, it can beprovided using a wire bond 24 to a corresponding pad on interconnectioncircuit 23 a. Solder elements 25 a and 25 b are lines of solder thatprovide a hermetic seal at the edges of coolant channel 15. Similarly,solder elements 26 a and 26 b are lines of solder that seal at the outeredges of coolant channel layers, thus keeping feedthroughs like 27 adry. Solder elements 26 c and 26 d are also lines of solder; in thiscase their function is to keep the interior of module 11 dry.Feedthroughs like 27 b within module 11 have a slightly differentstructure from feedthrough 27 a. Solder bump 28 connects between twocopper feedthroughs with no interconnection circuit present. Conversely,solder bump 29 connects to a trace on interconnection circuit 23 bthrough a copper pad 30 embedded in the interconnection circuit. Notethat interconnection circuits of the current invention include polymerdielectric layers that are not impervious to water; thus they are notpresent at the hermetic sealing elements.

FIG. 3 corresponds to section AA of FIG. 2. Copper base plate 14 isshown, together with solder features 25, 26, and 28 defined in FIG. 2.Coolant flow is unobstructed in the direction shown, 31.

FIG. 4 shows a variation of FIG. 3 wherein some of the solder bumps havebeen replaced with optical connections to increase the I/O bandwidth ofmodule 11 of subsystem 10. Optical fibers 41 a and 41 b are shown. Forexample, circuit 42 may implement an optical receiver and circuit 43 mayimplement an optical transmitter. Again, coolant flow 31 isunobstructed.

FIG. 5 illustrates in cross-section an expanded view of optical circuit42 of FIG. 4, including optical fiber 41 a and light path 51.Electro-optic chip 12 c is directly attached to interconnection circuit23 c using PIW flip chip connectors 52, to be further described. Forimproved heat dissipation, chip 12 c may be increased in height toprovide cooling through the back face of the die to copper substrate 14b, or alternatively, a copper slug like 20 of FIG. 1 may be employed. Aclear glass window 53 is provided in copper substrate 14 a fortransmitting light signal 51. Glass window 53 is sealed in substrate 14a using a glass seal 54, to be further described. An alignment cap 55 isused to position the end of fiber optic cable 41 a in proper relation toelectro-optic chip 12 c. Hermetic structure 56 a seals an edge ofcoolant channel 15, and hermetic structure 56 b seals the complement ofchips provided in subsystem 11 b. Filler materials 57 a and 57 b areused to stabilize the structures after assembly; they are non-conductingand preferably good thermal conductors. A disadvantage of module 11 bcompared with module 11 of FIG. 1 is increased difficulty of rework,owing to the presence of filler 57 b. Another disadvantage is the lackof a hermetic environment for electro-optic chip 12 c. However,providing high bandwidth optical connections is important enough thatthese disadvantages may be acceptable.

Optical alignment of light path 51 with electro-optic chip 12 c can beaccomplished in two steps. First, the basic alignment accuracy of thePIW connectors is around ±5 μm. A performance parameter of the opticallink (such as signal to noise ratio, SNR) is monitored while the solderis melted and the fine positioning of the chip attachment is optimizedfor link performance. The initial alignment and the fine-tuning featuredepend on features of the PIW connector, to be further described.

FIG. 6 is a further expanded cross-sectional view of a preferred directchip attachment of electro-optic chip 12 c with interconnection circuit23 c. In FIG. 6 this attachment includes a combination of heat bumps 61and input/output (I/O) bumps 62 as shown. The heat bumps are denselypacked for maximum heat conduction and the I/O bumps are spaced apart tocreate separate electrical connections, to be further described. Heatbumps 61 terminate on a copper pedestal 63 while I/O bumps 62 terminatein interconnection circuit 23 c.

FIG. 7 shows a variation on the fiber optic attachment depicted in FIG.6. A precisely located and aligned hole 71 is provided in coppersubstrate 14 b for capturing the end of optical fiber 41 a whileproviding good alignment of light path 51 as it enters or exits fromelectro-optic chip 12 c. As will be further described, the process usedto machine copper substrate 14 b can create alignment hole 71 with aplacement accuracy of around ±1 μm using available milling machines.Using this placement accuracy together with a process for fine-tuningthe optical alignment, as described in reference to FIG. 5, good opticalalignment can be achieved while avoiding the cost of fabricating theclear glass window 53 shown in FIG. 6.

FIG. 8 shows a stacked subsystem architecture 80 of the currentinvention wherein each of the modules in the stack has a fiber opticconnection 81 for increased I/O bandwidth.

FIG. 9 illustrates the use of a semiconductor plug 91 for communicatinghigh bandwidth signals between interconnection circuits 23 d and 23 e ofmodule 11 c. Chips 12 d and 12 e are thinned to approximately one halfof the thickness of plug 91 so that the different chips fit welltogether in module 11 c as shown.

FIG. 10 is a schematic representation of plug 91 including copper bump(pillar) element 100, and feedthrough element 101. Various methods areknown in the art for creating feedthrough element 101 using eitherpolysilicon or copper as the feedthrough conductor. Detailed features ofbump element 100 will be further described.

FIG. 11 corresponds to section BB of FIG. 2; it is a cross-sectionrepresenting an interface between a chip and a substrate. A backgroundarray 111 of heat bumps is shown; it is comprised of copper columns thatare closely spaced for maximum heat conduction and bend individually torelieve stress at the interface. I/O bumps are arrayed in rows andcolumns like 112; the I/O bumps are spaced apart and connect tosubstrate nodes individually, as will be further described. The layoutshown in FIG. 11 represents a default or starting condition; it can beadjusted as required in response to routing issues and thermal issues.Note that the default layout shown in FIG. 11 provides a signalconnector within a millimeter or two of any location on the chip; thismeans that signal path lengths can be short, aiding high frequencyoperation.

FIG. 12 is an expanded cross-sectional view corresponding to section CCof FIG. 11. Heat bumps 61 and I/O bumps 62 are shown. Heat bumps 61terminate at the substrate in a common well 63 filled with conductivematerial. I/O bumps 62 terminate at the substrate in individual wells 64filled with conductive material.

FIG. 13 is a further expanded cross-sectional view corresponding toDetail D of FIG. 12. Both heat bumps 61 and I/O bumps 62 are slendercopper pillars that can flex to relieve stress at the interface. Thebumps are anchored on pads 135 located on the front face (active side)of chip 12 f. A preferred height-to-width ratio for both kinds of bumpsis 5-10. A preferred height is 100 μm, because calculations show thataround 32 μm of lateral translation is required at the edge of a largechip undergoing typical temperature cycles during manufacture; a heightof 100 μm provides enough extension and flexibility to accommodate thismotion. In addition to the lateral motion, about 6 μm of verticaltranslation is also required to relieve the interface stress, allowingan attached chip to remain flat; the columns are preferably flexibleenough that they will bend or buckle as required to relieve this stressin the vertical direction. A preferred pitch for the I/O connectors is80 μm, providing over 15,000 connectors per square centimeter. Thisdensity provides enough connectors for good localized powerdistribution. The extra connectors can also help to lower signalcross-talk, by surrounding each signal connector with a set ofnearest-neighbor GND or DC power connections. A preferred pitch for theheat bumps is 30 μm, providing over 100,000 bumps per square centimeter.A suitable plating resist for achieving these geometries is Clariant Exp100XT. It is a positive resist that is easily stripped after the coppercolumns are formed. The resist can be patterned with essentiallyvertical sidewalls at 100 μm thickness.

Common well 63 is provided for terminating the heat bumps at thesubstrate surface, and an individual well 64 for each I/O bump is shown.An example of an interconnection circuit 23 f is shown. The well layeris shown as 133. Heat bumps 61 thermally connect with a copper pedestal134 for maximum heat conduction from IC chip 12 f to copper substrate14. As will be further described, each bump originates at a pad like 135on the chip. Note that bumps 61 and 62 combine mechanical, electrical,and thermal functions. Mechanically they provide structural support,stress relief, and compliant resistance to vibration and shock.Electrically they provide low inductance connectors estimated at 0.1 nHper bump/well combination; thus they will support digital signaling ataround 20 Gbps and RF circuits operating at multi-gigahertz frequencies.Thermally they can dissipate heat flux ranging from 9 W/cm² for signalbumps alone, to 160 W/cm² for densely packed heat bumps, and to over1,000 W/cm² when copper slugs like 20 in FIG. 1 are employed. Thesecalculations assume a liquid coolant temperature of 10° C. and a maximumjunction temperature of 85° C. Without resorting to the use of copperplugs, or using them only sparingly, subsystems like 10 of FIG. 1 candissipate over 10 kW, while running efficiently and reliably. Thismulti-function performance can enable a new technology platform whereindigital and RF components are integrated using the same PIW connector.The preferred technology platform also includes copper substrates andhigh density interconnection circuits and test chips, to be furtherdescribed.

FIG. 14 shows the use of a damping layer 135 of dielectric material suchas polyimide, fabricated on chip 12 f and substantially filling thespace around pillars 61 and 62, except for ends of the pillars that areinserted into the wells. Damping layer 135 provides a compliant supportstructure that does not substantially interfere with thestress-relieving properties of the compliant pillars, yet providesadditional protection against shock and vibration, and adds anotherthermally conductive path to aid in transporting heat between chip 12 fand substrate 14.

This disclosure will now describe manufacturing processes for buildingthe preferred modules and subsystems, along with a test method and arework method for the stacked architecture.

FIG. 15 is a top view of a square copper panel 140, preferably measuring305×305×0.8 mm. Inscribed on panel 140 is a circular copper wafer 141that is 300 mm in diameter. Inscribed within wafer 141 are seventeencopper substrates 14 measuring 50×50 mm. These dimensions take advantageof available fabrication equipment for processing 300 mm semiconductorwafers; however, any practical size of panel 140, wafer 141, andsubstrate 14 are included in the current invention. Alignment marks 142are also provided; along with the wafer and substrate outlines they areinscribed (machined) into the copper surface during milling steps to bedescribed.

FIG. 16A-16F illustrates a process sequence for fabricating isolatedcopper feedthroughs, starting with copper panel 140. FIG. 16A shows avacuum hold-down surface 161 of a milling machine such as an H100available from LPKF Laser and Electronics, Wilsonville, Oreg., USA. Thismachine spins the cutting tool at 100,000 RPM and is capable of millingtracks as narrow as 0.0031 inches or 80 μm. It also has a repetitionaccuracy of ±1 μm. Copper panel 140 of FIG. 15 is affixed to vacuumsurface 161 using two mounting tapes that are pre-applied to the copperpanel. The first tape is preferably a thermal release tape such asRevalpha available from Nitto Denko, Tokyo, Japan. It has a thermalrelease temperature of 150° C. for example. After removing its liner,this tape includes thermal release layer 162 (which is adhesive) andbase polyester layer 163. The second applied tape has an adhesive layer164 and a porous backing layer 165. After mounting copper panel 140 tovacuum surface 161 using the two mounting tapes, the milling tool isprogrammed to cut cylindrical cavities such as 166 a and 166 b thatpenetrate into porous layer 165 but do not interfere with vacuum surface161. The preferred thickness of panel 140 is 0.8 mm and the preferredcavity width, w 167, is 0.1 mm.

FIG. 16B shows the effect of screening a glass frit material 170 intothe machined cavities. This process is preferably performed using avacuum table 171, which will help fill the cavities to the bottom.

FIG. 16C shows the result of activating the thermal release layer andremoving both of the tapes from the back side of copper panel 140. Thestiffness of the screened frit material is adequate to hold copperfeedthroughs 21 in position while both mounting tapes are released usinga hotplate.

FIG. 16D shows the result of firing the glass frit to form glass seals22 around copper feedthroughs 21, as first defined in FIG. 2. An inertatmosphere is used for this firing at around 550° C., to preventexcessive oxidation of base copper panel 140. The screened frit materialwill reduce in volume when fired, forming a cupped surface 172 as shown.Copper wafer 141 b will be separated from the copper panel 140 using themilling tool, employing alignment marks 142 previously described inreference to FIG. 15. Chemical mechanical polishing (CMP) will beapplied as is known in the art, to polish the separated copper wafer toa final preferred thickness of 0.6 mm.

FIG. 16E shows an under bump metallization (UBM) 173 applied to thecopper feedthroughs as shown. UBMs are known in the art; a typicalformulation includes a thin titanium layer for adhesion, nickel as adiffusion barrier, and gold to provide a solder wetting surface.

FIG. 16F shows copper substrate 14 with solder balls 16 formed on UBMlayer 173. Since the solder balls would prevent vacuum hold-down onchucks used for processing the interconnection circuits on copper wafer141 b, process steps described in relation to FIGS. 16E and 16F aredelayed until the interconnection circuits are completed. The solderballs may be formed using wafer level stencil printing, jettingprocesses, or electroforming, all known in the art. When the depositedsolder alloy is heated to melting, it is pulled into a spherical shapeby surface tension. After bumping wafer 141 b with solder balls, it canbe separated into individual module substrates 14 using the milling toolpreviously described.

FIG. 17A-17P illustrates a process sequence for fabricatinginterconnection circuits and a well layer on a copper wafer. FIG.17A-17E teaches the base processes for fabricating a single dualdamascene copper layer, of which five are included in the preferredembodiment of the current invention. For visual reference in FIG.17A-17P an edge 172 is shown, although this edge is not created untilwafer processing is completed and substrates 14 are separated from wafer141 c.

FIG. 17A shows the result of spin coating copper wafer 141 c with apreferred spin-on dielectric (SOD) material 171 called BCB(benzocyclobutene), which is well known in the industry. Polyimide maybe used in place of BCB. The preferred thickness is approximately 8 μm.

In FIG. 17B, layer 171 of BCB has been patterned using dual damasceneprocesses, forming via features 173 a and 173 b, and also trace features174. Either photolithographic methods or the imprinting method may beused to achieve this result; both are known in the art.

FIG. 17C shows the result of sputter deposition of a seed layer ofcopper 175, typically using a thin layer of titanium for adhesion to theunderlying BCB.

In FIG. 17D, the copper seed layer has been electroplated, terminatingin an uneven surface 176.

FIG. 17E shows the result of polishing the surface of wafer 141 c usingCMP methods known in the art. Power trace layer 177 is complete,including vias 178 and 179, also traces 180. In the preferredembodiment, this layer provides GND plus two power supplies, deliveredusing via/trace 179 and traces 180 a and 181 a respectively. These powertraces repeat across the substrate surface, and trace 181 b delivers thesame voltage as 181 a. For the special case of the power trace layer 177depicted in FIG. 17E, embedded capacitance may be valuable for bypassingeach power supply to GND. Consequently, a high dielectric material maybe used for layer 171 instead of BCB or polyimide. This embeddedcapacitance technique is also known in the art.

FIG. 17F shows that a new layer 184 of SOD material has been applied towafer 141 c, in preparation for fabrication of a second dual damascenecopper interconnect layer.

FIG. 17G shows completed second layer 185 which is a GND layer, tosupport a transmission line structure for the subsequent signal layer,as is known in the art. Layer 185 includes ground conductors 186 andfeedthrough vias 187.

FIG. 17H depicts first signal layer 188, including traces 189 thatpreferably run in the x-direction. Signal traces are routed around thepower and GND vias.

FIG. 17I shows second signal layer 194, including traces like 195 thatpreferably run in the y-direction.

FIG. 17J illustrates layer 196, including vias 197 that will connectwith wells, to be fabricated next.

FIG. 17K illustrates a patterned dielectric layer 201, preferably around20 μm thick, forming the well shapes for a well layer, 200 a.

In FIG. 17L, well layer 200 b includes sputter deposited Ti/Au 202 thatphysically and electrically connects with the underlying copperstructures. An outer covering of gold is required for compatibility withthe preferred 80Au20Sn solder paste. For reliable solder connections,the Au layer must be at least 1000 Angstroms thick.

FIG. 17M shows the result of CMP to remove the Ti/Au thin films in fieldareas 203, providing electrical isolation between the wells in layer 200c.

In FIG. 17N, layer 200 d shows that the wells have been filled with fineconductive particles 204. The preferred particles are made from agold-tin alloy, 80Au20Sn. The preferred particle diameter is smallerthan 4 μm, for easy filling of the wells 64. 80Au20Sn alloy islead-free, and has a successful history as a high-reliability solder.Any oxide tarnish on the particles can be removed by dipping in dilutehydrochloric acid; thus providing a flux-free solder. The wells arefilled by pouring the conductive powder over the substrate surface tofill all of the wells, then applying and removing a sheet of adhesive tothe substrate surface to remove loose particles adhering to areas 203between the wells.

FIG. 17O shows the result of aligning an IC chip 12 g with the substratecontaining the wells, bringing them together, and pushing gently on chip12 g so that the pillars 62 penetrate the powder in the wells. Forfragile chips such as ones using delicate low-k dielectrics, it may bedesirable to apply ultrasonic shaking, so that the pillars enter thepowder in the wells using only gravity as a pushing force. The alignmentprocess is known in the art: a precision flip chip aligner using splitbeam optics can achieve alignment accuracy of around ±2 μm. 80Au20Sn isreported to have tensile strength and shear strength of 40,000 PSI, thehighest of commonly available solders. This strength is advantageous forcapturing the ends of copper bumps 62 in wells 64 firmly undermechanical stress conditions such as occur during temperature cycling orshock conditions.

FIG. 17P shows the result of melting and flowing the 80Au20Sn solder atapproximately 320° C.; the volume of solder shrinks slightly.

In the event that a large subsystem like 10 of FIG. 1 begins to fail,some disassembly may be required. The resident test chips can be used toisolate which of the modules is defective and needs replacement orrepair. FIG. 18 shows schematically how the nozzles of a rework devicecan direct jets of hot inert gas selectively at a particular set offeedthroughs in the stack. Soldered joints at the chosen level in thestack will melt, allowing disassembly. This process may be aided byflowing hot inert gas through adjacent cooling channels 15. It ispreferable to suck out any solder remaining at the interface and replaceit with new solder on the replacement parts. The new solder is reflowedto semi-permanently install the replacement module. Defective modulescan be repaired by re-working defective chips using the processpreviously described in relation to PIW connectors.

A stacked 3D electronic subsystem has been described. It can achieve aminiaturization factor of over 100 compared with equivalent assembliesusing current technology, yet it can be well-tested, repairable, andadequately-cooled. The described methods can be applied to increaseperformance and reduce cost in assemblies as small as cell phones and aslarge as supercomputers.

1. A method for building a scalable electronic system or subsystemcomprising the steps of: a) fabricating a stackable module; b) stackinga plurality of said modules to form said system or subsystem with acooling channel provided between each pair of modules; and, c)circulating a coolant in said cooling channel.
 2. The method of claim 1wherein said stackable module is fabricated on a copper substrate. 3.The method of claim 2 and including the step of testing each of saidstackable modules prior to said stacking.
 4. The method of claim 3 andfurther including the step of re-working any defective chips in each ofsaid tested modules prior to said stacking.